1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a configuration of a data reading section in a non-volatile semiconductor memory device storing information in a non-volatile manner. More particularly, the present invention relates to a semiconductor memory device capable of correctly reading data even when a characteristic of a memory cell is deteriorated.
2. Description of the Background Art
A non-volatile semiconductor memory device storing data in a non-volatile manner has been known as one of semiconductor memory devices. A memory cell of the non-volatile semiconductor memory device is constituted of one transistor. Data is stored by accumulating electric charges in a charge accumulating region electrically isolated from the surroundings of the memory cell transistor to change a threshold voltage of the memory cell transistor. Since electric charges (referred to as charges simply hereinafter) are stored in a charge accumulating region isolated electrically from the surroundings, even if a power supply is cut off, the charges continue being accumulated in the charge accumulating region and data can be stored in a non-volatile manner.
FIG. 20 is a diagram schematically showing a sectional structure of a conventional non-volatile memory cell. In FIG. 20, the non-volatile memory cell includes: impurity regions 901 and 902 formed spaced apart from each other on a surface of a semiconductor substrate region 900; a charge accumulating region 903 formed above a channel forming region between impurity regions 901 and 902; and a control gate electrode 904 formed above charge accumulating region 903. Charge accumulating region 903 is constituted of a floating gate made of polysilicon or the like, or of a nitride film. In a case where charge accumulating region 903 is constituted of a nitride film, oxide films are formed between charge accumulating region 903 and control gate electrode 904, and between charge accumulating region 903 and substrate region 900.
In a construction of a non-volatile memory cell shown in FIG. 20, accumulation of charges (an electron is indicated by exe2x88x92) into charge accumulating region 903 is performed in the following way. That is, impurity region 901 is supplied with a high voltage in the range from 4 V to 5 V, for example, while impurity region 902 is maintained at ground voltage level. Control gate electrode 904 is applied with a voltage in the range from 5 V to 6 V.
In this state, a channel region 905 is formed at the surface of the substrate between impurity regions 901 and 902 and a current I flows from impurity region 901 to impurity region 902. Current I flowing in channel region 905 is accelerated by a high electric field formed in the vicinity of impurity region 901 (drain region) to form hot electrons. The hot electrons are accelerated in a direction toward charge accumulating region 903 by a high voltage applied to control gate electrode 904 and injected into charge accumulating region 903. In a case where charge accumulating region 903 is formed of polysilicon or the like, injected electrons move over an entire of charge accumulating region 903. In a case where charge accumulating region 903 is constituted of a nitride film or the like, electrons trapped in charge accumulating region 903 do not move over a long distance to be localized in the vicinity of impurity region 901.
A state where electrons have been injected into charge accumulating region 903 is hereinafter referred to as written state (programmed state). In the written state, since electrons are accumulated in charge accumulating region 903, the memory cell transistor has a high threshold voltage (provided that the memory cell transistor is of an N-channel type).
FIG. 21 is a diagram showing an example of applied voltages to a memory cell when electrons are extracted from charge accumulating region 903. There are various ways for erase operations. In FIG. 21, there are shown applied voltages employed in a substrate erasure method in which electrons are ejected into a substrate region.
In FIG. 21, when electrons are extracted from charge accumulating region 903, control gate electrode 904 is supplied with, for example, a negative voltage of xe2x88x925 V and impurity regions 901 and 902 are supplied with a voltage in the range from 5 to 6 V. In this case, substrate region 900 is supplied with a voltage at a level similar to the voltage of impurity regions 901 and 902. In this state, electrons (exe2x88x92) accumulated in charge accumulating region 903 are ejected to substrate region 900 through a Fouler-Nordheim (FN) tunnel current. This state is usually called an erased state, where a threshold voltage decreases.
As an erase operation for a non-volatile memory cell, there are available a method in which channel hot holes are injected into charge accumulating region 903, and a method in which electrons are extracted from charge accumulating region 903 to gate electrode 904 and others.
By a quantity of charges stored in charge accumulating region 903, as shown in FIGS. 20 and 21, a threshold voltage of the memory cell transistor changes, and the threshold voltage is correlated with data. Therefore, since a threshold voltage changes consecutively according to a quantity of electric charges stored in charge accumulating region 903, the non-volatile memory cell can store multi-valued data.
FIG. 22 is a diagram schematically showing applied voltages when data is read from the non-volatile memory cell. In FIG. 22, control gate electrode 904 is supplied with a read voltage Vread, while impurity region 901 is supplied with ground voltage. Impurity region 902 is supplied with a bit current Ib1. Read voltage Vread is set to an intermediate voltage level between threshold voltages in erased state and written state, or a voltage level higher than a threshold voltage in written state.
When read voltage Vread is set to an intermediate value between a threshold voltage in erased state and that in written state, the memory cell transistor in erased state is turned on, while the memory cell transistor in written state is turned off. Substantially no bit current Ib1 flows through the memory cell in the written state.
When read voltage Vread is set to a voltage level higher than a threshold voltage in the written state, a current flows through the memory cell in any of erased state and written state. Threshold voltages in erased state and written state are different from each other, and therefore, a channel resistance of the memory cell transistor is different according to whether the memory cell transistor is in the erased state or in the written state, and a current flowing through the memory cell transistor is made different in magnitude, accordingly. Therefore, by detecting a quantity of current through a bit line, a state of the memory cell, or stored data can be detected.
FIG. 23 is a diagram schematically showing data storage regions in a case where charge accumulating region 903 is constituted of a nitride film. In FIG. 23, in a case where charge accumulating region 903 is constituted of a nitride film, an oxide film 908 is formed between control gate electrode 904 and charge accumulating region 903 and an oxide film 909 is formed between charge accumulating region 903 and semiconductor substrate region 900. In charge accumulating region 903, there are formed data storage regions BTR and BTL. In a case where charge accumulating region 903 is made of a nitride film, an electron mobility is very low, and the data storage regions are formed being localized in charge accumulating region 903. When electrons are injected into data storage region BTR (right bit region), a current I is conducted from impurity region 902 to impurity region 901. In this state, hot electrons are generated by a high drain electric field formed in the vicinity of impurity region 902 and the hot electrons are accelerated by a high electric field formed by a voltage on the control gate and trapped in data storage region BTR of charge accumulating region (nitride film) 903.
When electrons are injected into data storage region (left bit region) BTL, a current is conducted from impurity region 901 to impurity region 902. Hot electrons are generated by a high drain electric field formed in the vicinity of impurity region 901 and electrons are accumulated into data storage region (left bit region) BTL of charge accumulating region 903.
When data stored in right bit region BTR is read, current I is conducted from impurity region 901 to impurity region 902. In this case, in the vicinity of impurity region 901, a punch-through occurs by a drain high electric field and a depletion layer is merely widened. Electrons stored in left bit region exerts no influence on a channel current and a current flows from impurity region 901 to impurity region 902 according to a quantity of electrons stored in right bit region BTR.
In contrast, when data stored in left bit region BTL is read, a current is flowed from impurity region 902 to impurity region 901. In this case, in the vicinity of impurity region 902, a punch-through occurs by a drain high electric field and electrons stored in data accumulating region (right bit region) BTR exerts no influence on reading storage data from data storage region BTL. Therefore, a quantity of current flowing from impurity region 902 to 901 is determined according to a quantity of electrons stored in left bit region BTL.
In a case where a nitride film is used as charge accumulating region 903, two data storage regions BTR and BTL can be formed in 1-bit memory cell. Therefore, a multi-valued memory cell can be implemented, which stores 2 bit data in one-bit memory cell, thereby enabling a large capacity memory device to be achieved in a small occupation area.
In a non-volatile memory cell, a high electric field is applied to accumulate electrons in charge accumulating region 903. Therefore, if writing/erasing are repeatedly performed, an insulating film in an electron accumulating region or in an electron passing-through region would be deteriorated, to cause a problem of a change in data holding characteristic of a memory cell. Deterioration in memory cell characteristic associated with increase in number of write/erase cycles of a memory cell transistor occurs in a collective erase type memory (flash memory) having a charge accumulating region made of polysilicon and in an insulating film electric charge trapping memory trapping electrons in an insulating film. In a memory device storing data by trapping electrons in an insulating film, however, a quantity of accumulated electrons is smaller compared with that in a general stacked gate transistor having a polysilicon floating gate. Therefore, such deterioration in data retention characteristic would be more remarkable as the increase in number of write/erase cycles. First, description will be given of a case of an insulating film charge trapping type memory device having a charge accumulating region formed of an insulating film.
When an erase/write is repeated, a threshold voltage of a memory cell in the written state is some case rendered lower than a threshold voltage in the written state at an initial stage. As causes for such decrease of the threshold voltage, the following may be considered. An excessively decreased threshold voltage in erasure reduces the threshold voltage after writing by the excessively decreased amount. Electrons trapped in an insulating film leak out due to deterioration in the insulating film and an oxide film to lower the threshold voltage. Furthermore, in a case of the leakage of electrons, electrons would be trapped in an oxide film to reduce the a voltage applied on a control gate in writing effectively, and a sufficient electric field is not applied between a nitride film and a substrate region, to hinder accumulation of a sufficient amount of electrons in the charge accumulation.
In contrast, a case exists where after an erase/write is repeated, a threshold voltage of a memory cell in erased state is raised to be higher than a threshold voltage of a memory cell in erased state at an initial stage. As for causes for this phenomenon, the following phenomena may be considered. Electrons accumulated in a nitride film move toward the center of the nitride film and a quantity of electrons accumulated in the central portion of the nitride film is increased as the number of cycles increases, thereby raising a threshold voltage of the memory cell. As the second, electrons are continuously kept being trapped in an oxide film and electrons can not be extracted from the nitride film sufficiently.
In U.S. Pat. No. 6,222,768, for example, there are proposed a construction for performing writing, erasure and reading data with correctness while compensating for deterioration in memory cell characteristic (a change in threshold voltage characteristic) occurring with increase in number of write/erase cycles.
FIG. 24 is a diagram schematically showing a configuration of a main part of a non-volatile semiconductor memory device shown in the above described prior art reference. In FIG. 24, the non-volatile semiconductor memory device includes: a memory cell array 910 having a plurality of non-volatile memory cells arranged in rows and columns; an I/V converter 912 converting a current Imen flowing through a bit line having a selected memory cell in the memory cell array 910 connected to a voltage Vmem; a reference current generating circuit 915 for generating a reference current Iref; an I/V converter 917 for converting reference current Iref to a reference voltage Vref, and a comparator 920 for comparing reference voltage Vref with memory read voltage Vmem to generate a signal indicating a state of a memory cell according to a result of the comparison.
In the configuration shown in FIG. 24, current Imem flowing through selected memory cell in memory cell array 910 is converted into memory read voltage Vmem by I/V converter 912 and memory read voltage Vmem is compared with reference voltage Vref converted by I/V converter 917, and determination is made on whether the memory cell is in erased state or in written state.
FIG. 25 is a diagram schematically showing a configuration of memory cell array 910 shown in FIG. 24. Memory cell array 91 has nonvolatile memory cells MC arranged in rows and columns, and in FIG. 25, there are shown memory cells MC arranged in two rows and three columns representatively. Word lines WL0 and WL1 are provided corresponding to respective rows of memory cells MC and bit lines BL0 to BL3 are provided correspondingly to columns of memory cells MC.
Bit lines BL0 to BL3 each are shared by memory cells on adjacent columns. A memory cell MC is constituted of an insulating film charge trapping memory cell and has data storage regions BTR and BTL.
Bit lines BL0 and BL2 are coupled to a global bit line GBLA through select gates TG0 and TG1, respectively and bit lines BL1 and BL3 are coupled to a global bit line GBLB through select gates TG2 ad TG3, respectively. Select signal SL0 to SL3 are applied to select gates TG0 to TG3, respectively.
Each of bit lines BL0 to BL3 is formed of a diffusion layer. Since no contact is provided for connection of a memory cell to a bit line in the memory cell array and a bit line is formed by memory cells on adjacent columns, an occupation area of a memory cell is 4xc3x97F2. Here, F indicates the minimum design size. A pitch of bit lines and a pitch of word lines are both indicated by F. Since one memory cell MC stores 2 bit data, an effective memory cell area is 2xc3x97F2.
In data reading (including a verify operation), bit lines each connecting to a selected memory cell are connected to global bit lines GBLA and GBLB. One of global bit lines GBLA and GBLB is supplied with power supply voltage according to which stored data of data storage regions BTL and BTR is read out. The other global bit line is coupled to I/V converter 912 as described later.
Power supply voltage is transmitted to a selected bit line (a bit line located farther away from a data storage region) through corresponding select gates TG0 to TG3. A voltage at the drain of a memory cell connected to the select bit line is at a voltage level lower than power supply voltage by a threshold voltage of the select gate because of a threshold voltage loss in the select gate. A current flows in the memory cell according to stored data owing to the drain voltage. In FIG. 25, there is typically shown a path through which global bit line GBLA is supplied with power supply voltage and memory cell current Imem flows into global bit line GBLB through bit lines BL2 and BL1.
Global bit line GBLB is further selected by a column select gate not shown and coupled to I/V converter 912 shown in FIG. 24.
In the prior art, when a verify failure occurs in a verify operation after erasure, erase and verify operations are repeatedly performed till the number of times of erase pulse application reaches the maximum number thereof. When the number of times of verify failures reaches the maximum allowable number, reading is performed on a threshold voltage of a reference memory cell stored in a register provided in a reference current generating circuit 915. The reference memory cell is placed outside the memory cell array, is in the erased state due to the erasure during erase verify operation and data indicating a threshold voltage of the reference memory cell is stored in the register. The threshold voltage of the reference memory cell can be incremented (a write operation is performed) till the threshold voltage of the reference memory cell stored in the register reaches the maximum value.
Voltage levels of a read voltage and a verify voltage outputted by I/V converter 917 are determined according to a threshold value of the reference memory cell. Therefore, as shown in FIG. 26, when the number of times of verify failures reaches the maximum allowable number, a reference voltage window for the memory cell is changed. In FIG. 26, there is shown, by way of example, a state where reference voltages Vref for writing, reading and erasure of 3 V, 2 V and 1 V, respectively are incremented, after adjustment, to 3.2 V, 2.2 V and 1.2 V, respectively.
Even if a write/erase cycle is repeatedly performed and memory cell characteristics are deteriorated to vary the threshold voltage, by changing reference voltage Vref window, a reference voltage window adapted to the varied memory cell characteristics can be produced intending to perform write/erasure correctly.
In the above conventional construction, a threshold voltage of a reference memory cell is incremented by a prescribed step to perform a further erase verifying when an erase verify failure occurs a prescribed number of times in an erase cycle. Therefore, a window of a threshold voltage for a memory cell of an erasing target is shifted when an erase verify failure occurs
The shift in threshold voltage is performed commonly on all of memory cells, standing on the premise that as the number of times of writing/erasure increases, threshold voltages of all of the memory cells rises uniformly.
Memory cells are, however, not the same in number of times of writing/erasure (rewriting), but are variant in the number times of rewriting as well as in memory cell characteristic. Therefore, even the memory cells storing data of the same logical level have variant threshold voltages
Accordingly, in a case where a window of a verify voltage is increased, there exists a memory cell having a relatively low threshold voltage even in the written state among the memory cells not subject to rewriting. Therefore, read failure is likely to occur due to margin shortage when a window of verify voltages is shifted in common to all the memory cells.
Specifically, consideration is now given of a distribution of memory cells storing data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d as shown in FIG. 27. Data xe2x80x9c1xe2x80x9d corresponds to the erased state and memory cells storing data xe2x80x9c1xe2x80x9d each have a threshold voltage between an upper side erase verify voltage Veu and a lower side erase verify voltage Vel.
A memory cell storing data xe2x80x9c0xe2x80x9d corresponds to a memory cell in the written state (programmed state) and has a threshold voltage equal to or higher than lower side write verify voltage Vp1.
When data is read, by way of example, read voltage Vread, at a voltage level between upper side erase voltage Veu and lower side write verify voltage Vp1, is applied. Under this state, a window of a verify voltage and a read voltage are applied. A threshold voltage of a memory cell subject to rewriting shifts in the high voltage direction in FIG. 28 with respect to the voltage V both in the erase region and in written region. A memory cell not subject to rewriting has a threshold voltage unchanged. Here, rewriting indicates an erase operation or a write operation.
In FIG. 28, since a verify voltage is shifted, upper side erase verify voltage Veus and lower side write verify voltage Vp1s are used. Instead of read voltage Vread, a shifted read voltage Vreads is used according to a shift in the verify voltage. All memory cells have the storage data rewritten in the same rewrite cycle, but an addressed memory cell has the storage data rewritten. Therefore, a threshold voltage distribution is further broadened in width compared with a state shown in FIG. 27. Among the memory cells in the written state, a memory cell with a relatively low threshold voltage in written state is small in difference between the threshold voltage thereof and shifted read voltage Vreads, and small in margin for data reading, impeding correct data reading.
Furthermore, since a verify voltage window is shifted uniformly for all of memory cells, a memory cell, small in number of times of rewriting and causing no deterioration of memory cell characteristic, has a threshold voltage thereof sifted upward to a higher voltage. Therefore, when a memory cell, smaller in number of times of rewriting, in the erased state is set into written state, a shift amount in threshold voltage is greater as compared with a memory cell greater in number of times of rewriting, and accordingly has an increased number of times of rewrite pulse application. Accordingly, a characteristic of an insulating film of a memory cell smaller in number of times of rewriting tends to be deteriorated. In other words, when a verify voltage window and the read voltage are shifted commonly for all of memory cells, a characteristic of a memory cell small in number of times of rewriting is adjusted according to a characteristic of a memory cell greater in number of times of rewriting. Therefore, characteristics of all of the memory cells in the non-volatile semiconductor memory device are set according to the worst memory cell characteristic, resulting in promotion of deterioration in characteristics of memory cells as a whole.
In this prior art technology, a threshold voltage of a reference memory cell is changed by a prescribed step in reference current generating circuit 915. In this prior art reference, however, no detailed description is given of how a threshold voltage of the reference memory cell in reference current generating circuit 915 is shifted. With increase in the number of times of rewriting, the reference memory cell transistor has the memory cell characteristic changed. Therefore, an amount of shift would be varied even by application of the same rewrite pulse, and therefore, desired threshold voltage shift could not be provided correctly at all times.
In this prior art reference, the reference memory transistor for generating a reference current is provided for reading, for writing and for erasure separately. In a case where a plural kinds of such reference memory transistors are provided outside the memory cell array and have the respective threshold voltages adjusted in accordance with an operation mode, the control becomes complex. In addition, it is very difficult to form memory cell transistors the same in characteristic as memory cell transistors outside the memory cell array. This is because a peripheral layout pattern of the reference transistors is greatly different from that of the memory cell array section.
Furthermore, in this prior art reference, consideration is given only to a threshold voltage shift in a higher level direction with the increase in number of times of rewriting, and no consideration given to the phenomenon that a threshold voltage of a memory cell in written state is reduced below a desired value due to deterioration in insulating film. Therefore, in a case where a threshold voltage in written state is decreased due to a change in memory cell characteristic with increase in number of times of rewriting, there is a possibility that the written state of such memory cell is erroneously determined as the erased state when shifted read voltage Vreads as shown in FIG. 28 is applied
The above problem also similarly arises in a case where read voltage Vread is set to a level higher than a threshold voltage of a memory cell in written state and a difference between currents of the memory cells in written state and in erase state is utilized. Specifically, in a construction in which a voltage for data reading including a verify operation is set commonly to all of memory cell, a threshold voltage difference would be small between a memory cell having a highest threshold voltage among the memory cells in the erase state and a memory cell having a lowest threshold voltage among the memory cells in the written state, and data can not be read correctly. In other words, in data reading, a reference current (or a reference voltage) in reading is set to an intermediate level between a current flowing in a memory cell in the erased state and a current flowing in a memory cell in the written state. In such a construction, when the reference current is shifted toward a higher level, a difference between a memory cell current flowing in a memory cell in the written state and the reference current becomes smaller, and correct reading of data could not be achieved.
The issue of the above deterioration in memory cell characteristic associated with increase in number of times of rewriting similarly occurs in a memory cell having a polysilicon floating gate, since deterioration occurs in a tunnel insulating film with increase in the number of times of rewriting.
It is an object of the present invention to provide a semiconductor memory device capable of correctly reading stored data in a memory cell.
It is another object of the present invention to provide a non-volatile semiconductor memory device capable of correctly reading data in accordance with a comparison with a reference current regardless of the number of times of rewriting of a memory cell.
A non-volatile semiconductor memory device according to a first aspect of the present invention includes: a plurality of non-volatile memory cells, each formed of a memory cell transistor having a threshold voltage changed in accordance with stored data, for storing data in a non-volatile manner; a detection circuit for detecting and storing a change in threshold voltage characteristic of the plurality of non-volatile memory cells; a read circuit for reading stored data in a selected memory cell of the plurality of non-volatile memory cells in accordance with comparison of a read current corresponding to a current flowing in the selected memory cell and a reference current; and a reference current control circuit for setting a quantity of the reference current in accordance with a result of the detection by the detection circuit.
A semiconductor memory device according to a second aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; a plurality of bit lines, provided corresponding to the memory cell columns, each connecting to the memory cells on a corresponding column; a plurality of sense amplifiers coupled commonly to a selected bit line coupled to an addressed memory cell, for amplifying data in the addressed memory cell appearing on the selected bit line when activated; and a sense control circuit for controlling operations of the plurality of sense amplifiers in different ways from each other.
A semiconductor memory device according to a third aspect of the present invention includes: a plurality of memory cells; a reference circuit for generating and outputting reference data; an internal read circuit for comparing data read from a selected memory cell out of the plurality of memory cells with the reference data and reading data in the selected memory cell on the basis of a result of the comparison; and a reference data change circuit for selectively changing, in a specific operation mode, selectively set conditions for reference data outputted by the reference circuit in accordance with an address signal of the selected memory cell.
By detecting and storing a change in threshold voltage characteristic of a memory cell to selectively change a reference current serving as a reference for data reading in accordance with a result of the storage, a reference current corresponding to a state of a selected memory cell can be generated. Individual memory cell data can be read out with a sufficient margin for a read current ensured. Accordingly, data can be correctly read even in deterioration of a memory cell characteristic, regardless of a change in threshold voltage characteristic without exerting an adverse influence on reading data from a normal cell.
Furthermore, a plurality of sense amplifiers are commonly to a selected bit line and are made different in control manners from each other. Thus, a so-called xe2x80x9cmulti-sensingxe2x80x9d can be performed and data can be read correctly. In addition, a state of a threshold voltage of a memory cell can be identified accordance with coincidence/non-coincidence between output signals of the plurality of sense amplifiers. Accordingly, a memory cell having a threshold voltage shifted with respect to data at the same logical level can be detected and an appropriate measure can be taken for such detected memory cell. Moreover, by changing the set conditions for reference data in a specific operation mode on the basis of an address of a selected memory cell, read conditions meeting a characteristic of each individual memory cell can be set, and memory cell data can be read correctly without exerting an adverse influence on reading data from a normal memory cell even when a memory cell is deteriorated in characteristic.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.